• Successful validation of a key sub-process within the pre-clean sequence
• Confirms the Company's process architecture is performing to design expectations
• Represents a step toward enabling direct graphene growth on semiconductor wafers

Adisyn Ltd (ASX: AI1) has announced that its wholly owned subsidiary 2D Generation (2DG) has successfully achieved the initial phase of developing a wafer (or coupon level) surface pre-clean step, one of several sub-processes within the overall pre-clean stage of its proprietary low-temperature graphene deposition process. This achievement represents an important technical milestone in Adisyn's program to develop a repeatable, scalable, low-temperature graphene deposition process, aimed at enabling the next generation of graphene-based semiconductor interconnects. The pre-clean stage is the first and one of the most crucial elements of Adisyn's graphene growth sequence, preparing the wafer surface for atomic-scale film deposition by removing residual contamination and optimising surface chemistry. 2DG's research team has now successfully validated one of the major sub-processes within this stage, demonstrating that the Company's low-temperature pre-treatment can effectively prepare wafer surfaces for subsequent graphene deposition. This achievement confirms that the Company's process architecture is operating as expected and provides confidence to proceed into the next major experimental phase, which will involve commencing extensive deposition trials, refining the remaining sub-processes within the pre-clean stage, and optimising deposition parameters. Adisyn's graphene program is being driven by a multi-disciplinary team of more than 20 experts across Israel, Europe and the United States, with key support from leading institutional and industry partners, including Tel Aviv University, imec, and the EU Connecting Chips Initiative.

Over the coming quarters, Adisyn will continue iterative development across all pre-clean parameters, undertake broader coupon testing of graphene precursor candidates and their deposition parameters, and begin evaluating scalability and wafer-level deposition. The Company remains on track to deliver progressive technical validation through 2025 and into early 2026.