• Execution Plan progression: Ultra-Edge Modular Design and Build program
• Three-Layer Modular Hardware Architecture: Sensing, Compute, Memory
• Ultra Low power target: Sub-1mW power budgets for autonomous devices

dorsaVi Limited (ASX: DVL) is pleased to announce the commencement of its Ultra-Edge Modular Design and Build program, the third workstream in the Company's five-stage Execution Plan. This program represents a critical transition point as the Company has spent the past period proving the science, securing IP licences and validating its RRAM memory and neuromorphic processing technologies. The Ultra-Edge Modular Design program has four core workstreams: Modular Device Pack Architecture, Layer Separation, Power Architecture, and API Layer Development. The defining characteristic is its modular architecture, separating sensing, compute, and memory into distinct, interoperable layers. This modular approach provides flexibility to configure the platform for different applications and upgrade individual layers as the technology evolves. The power architecture is being designed specifically for in-memory compute, targeting sub-1mW operation for coin-cell battery-operated autonomous and wearable devices. An API layer is also being assessed to provide a clean, documented integration interface for partners to embed dorsaVi's ultra-edge intelligence stack. The program is being shaped by the hardware requirements of next-generation robotics and autonomous systems, including collaborative robots, autonomous drones, and industrial automation. Successful completion of the program positions dorsaVi to offer a manufacturable, partner-ready ultra-edge intelligence module that can be licensed, embedded, or deployed across its commercial target verticals.

The Ultra-Edge Modular Design program marks the point where dorsaVi's technology thesis begins to translate into a physical product. The modular architecture provides flexibility to configure the platform for different applications, upgrade individual layers as the technology evolves, and partner at the layer level. The integration interface is designed to enable partners to incorporate dorsaVi's sub-millisecond local inference capability within highly constrained power environments without needing to develop underlying semiconductor architecture themselves.